This invention relates generally to semiconductor memories.
Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, as an electronic memory. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between generally amorphous and generally crystalline local orders or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states.
Typical materials suitable for such an application include various chalcogenide elements. The state of the phase change materials is also non-volatile, absent application of excess temperatures, such as those in excess of 150° C. for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed. This is because the programmed value represents a phase or physical state of the material (e.g., crystalline or amorphous).
The memory cells can be selected for a reading operation, for example, by applying suitable voltages to the respective word lines and suitable current pulses to the respective bit lines. A voltage reached at the bit line depends on the resistance of the storage element, i.e., the logic value stored in the selected memory cell.
The logic value stored in the memory cell is evaluated by using sense amplifiers to detect a difference in voltage and current reflecting the state of the memory. Typically, a sense amplifier includes a comparator receiving the bit line voltage, or a related voltage, and a suitable reference voltage for comparison to the level from the memory, after a period. For example, where the bit line voltage is higher than the reference voltage after a period of time, the memory state stored is described as a reset or logic value “0”, whereas in the case in which the bit line voltage is lower than the reference voltage, the stored logic value is described as set or a “1”.
The access element can consist of a threshold switch made of a phase-change material, similar to the storage element serially connected thereto. This element switches (without changing its phase) from a high-resistance condition to a low-resistance condition when a voltage applied thereacross exceeds a threshold value and reverts to the high-resistance condition when a current flowing therethrough falls below a minimum holding value. A voltage across the access element in the low-resistance condition has a substantially constant value (holding voltage) because the dynamic resistance dV/dI is relatively low so most of the voltage drop is a holding voltage, Vh. In this case, the matrix of memory cells can be advantageously provided without any transistor, and then using a single technological process.
During a reading operation, the read current pulse causes the charging of stray capacitance intrinsically associated with the bit line, and, accordingly, a corresponding transient of the bit line voltage on a selected bit line. If charged positively, the respective bit line voltage raises towards a corresponding steady value, depending on the logic value stored in the selected memory cell.
The transient of the bit line voltage depends not only on the stray capacitances associated with the bit lines, but also on operative parameters of the storage elements and of the access elements, such as impedance and threshold/holding voltages. Accordingly, robust sense amplifiers for memories based on a phase-change material preferably will allow a large variability in those operative parameters of the storage elements and of the access elements, varying also with temperature. A problem is that such a variability usually involves a reduction in a discrimination margin between the reference voltage and a value of the bit line voltage to be compared thereto.
Furthermore, a variability in the threshold voltage of the access element brings an uncertainty on a time in which the access element is switched on and then on a time in which the bit line voltage reaches a steady-state value to be sensed. Accordingly, such a variability has to be taken into account for the timing of a reading operation. Inevitably, the reading operation is slowed down, since the timing has to be based on the worst cases. Also, to preserve cell state and avoid a “read disturb” state change during read or mis-read, the voltage across the memory storage area is preferably maintained at less than a maximum voltage, such as the threshold voltage of the memory element VTH (oum). To avoid exceeding this maximum allowed voltage, the current applied to the column may be less than desirable for rapid column charging, increasing read delay.
Thus, conventionally, the current to read phase change memories is limited to less than the threshold current of the memory element, Ith(oum) or the voltage forced is limited to avoid applying a voltage across the memory element higher than its threshold voltage, Ith(oum). However these techniques may respectively increase undesirably the read access times and/or the possibility of exceeding a current that avoids programming a set bit (read disturb). One reason for this limitation of read current is to prevent triggering of the phase change memory element, which may require refreshing the bit to meet the expected data retention times. Such refreshing (re-write after read) is undesirable for increasing the read cycle time and reducing bit endurance related to write cycles.
If the current flowing through the selected memory cell exceeds a threshold current value, Ith(oum), for example a few microamperes, a heating by a Joule effect of the storage element is caused when the voltage across the oum snaps back from Vth to Vh due to displacement current related to driving the column voltage, which, consequently, can spuriously program the selected bit from reset to set (read disturb). In order to avoid spurious programming of the storage elements, for example, the maximum read current forced into a selected column can be limited to a value lower than the threshold current.
Such a small read current if less than Ith(oum) may involve a relatively slow charging of the bit line stray capacitances, which implies an increase of the time required for a reading operation. In particular, in the case the memory that is adapted to perform reading operations in a burst way, an initial latency, i.e., a time range between a first time in which a first address is provided to the memory and a second time in which the first data read is output, is increased. The request for faster and faster reading operation consequently prefers smaller and smaller initial read access delay latencies from when the selected address is provided the chip until the data is available on the output. Delays in charging the selected column due to use of low read current increases this delay latency until the data is available on the output.
A solution for decreasing a duration of the reading operation in the burst way is to increase the number of sense amplifiers of the memory, but this increases as well the power consumption and the related semiconductor occupied area of the memory which increases chip cost.
Thus, there is a need to improve read access time and/or margins for a higher performance phase change memory.